Software tools are frequently used in the design of analog, mixed-signal and custom digital circuits. In front-end design for yield, designers choose device sizes such that the maximum possible percentage of manufactured chips meets all specifications (i.e., such the yield is maximized). The designer may have aims to improve performance as well (i.e. have more aggressive specifications). In order to effectively design such circuits, designers need insight into the design. Specifically, the designers need insight into how topology choice, device sizes, and layout affect performances and yield of the circuits in question. Current techniques to provide this insight include: examination of circuit schematics, manual derivation of modeling equations, and circuit simulation. These techniques typically divide the problem into the creation of data on which an analysis can be based, and on the visualization used to represent the data.
The data is often created using simulations making use of circuit simulation/analysis tools such as SPICE. The datasets generated can be generated in one of many possible ways. Examples of such common ways follow. The data set can be based on evaluating the performance of a single design point (e.g., device sizes), single random point (e.g., as drawn from a probability density function that approximates manufacturing variations), and single environmental point (e.g., specific setting for temperature & load). Alternatively, the data can be based on single or nested sweeps across design variables of a given circuit design to provide a better data set with which to work. A single sweep might be: sweep across a set of values v1, . . . , vi, . . . vN for a specific design variable with every other design variable fixed. Following this, a simulation is performed at {design point i, the “nominal” random point, a “typical” environmental point} to output a set waveforms and of performance values, such as measures of power consumption and gain. This provides a data set that can be used in multiple ways as will be described below. A nested sweep might be: outer sweep is across a set of values v1, . . . , vi, . . . vN for a specific design variable with every other design variable fixed; then for each design point, there is an inner sweep across a set of user-defined environmental points pi, . . . , pj, . . . pM. This is followed by a simulation done at that {design point i, nominal random point, environmental point j} to obtain corresponding output performance values. Alternatively, for a given design point, a “Monte Carlo” simulation can be performed as follows: at a given design point, for each of a set or random points drawn from a probability density function, for each of a set of user defined environmental corners, simulate and extract performance values. Sensitivity analysis can also be performed about a design point, random point or environmental point by causing slight perturbations in corresponding design variables, random variables, and environmental variables respectively.
The data obtained is typically presented to the designer as either raw data or in a simple data aggregation. A more “raw” form (i.e., less-processed form) of the data might be a waveform, for example of a voltage vs. time, which would be output from a single {design point, random point, environmental point} in a transient analysis. Or, if the dataset is the result of a sweep of a design variable at N different values, then there may be N waveforms overlaid on a same plot. An example of slightly more processed data is to have a performance value (e.g., power consumption) presented as a function of a design variable, i.e., the result of a sweep across that the given design variable. The results of a nested sweep where an outer sweep has values of a design variable and an inner sweep has environmental points could be a plot of “worst case performance” versus design variable values, where “worst case performance” for a design point is the worst of all performance values across environmental points extracted for that design point. The results of a Monte Carlo simulation might be analyzed by estimating yield, as the percentage of random points that are feasible, where a random point is feasible only if all its worst-case-performances (across environmental points) met all performance specifications. Another more visual way to analyze Monte Carlo results would be in a 2d scatter plot, where each axis is for a worst-case-performance such as worst-case gain and worst-case power consumption. Then there is one point drawn on the scatter plot for each random point. Such a scatter plot is useful to visually identify correlations among performances.
These visualization methods are suitable for a small set of data, which results in a requirement to constrain the number of variables that can be adjusted, the range of the variables, and the depth of nesting. If such limitations are not imposed, the number of possible plots presented quickly becomes overwhelming for the designer. In modern designs, there are a large number of design elements where each element may have many design and random variables associated with it. This means that there can be a huge number of variables. For example, 10 random variables per device, and 100 devices, means 1000 random variables. Moreover, these variables can be nonlinearly coupled: for example, 1000 variables could have about 1,000,000 possible couplings. Despite this, the designer wants to, somehow, get insights into how to design the circuit. To try to understand the whole space of possible variables and their relations is an extremely complex task for a human Even if a dataset to describe a given could be generated via the traditional sweeps, etc., that dataset would be so huge that it would be unusable for human analysis. One possibility to provide the designer with a more compact data set is to limit the number and range of variables to be adjusted. This results in a manageable data set, and allows a certain degree of design optimization, but it requires some prior insight into which variables to limit. Therefore, the chance for optimality is lost and, there is a risk that important information will not be presented to the designer.
One problem faced by designers is that there is typically a complicated nonlinear relation from each component's design and random variables to each performance characteristic, and ultimately to yield. For example, not every component that has an effect on the performance characteristics of a design will have an effect on the yield of the manufacturing process. Without a tool to provide information identifying which elements have an effect on yield, designers may make performance-changing modifications without realizing any gain in yield.
Another problem faced by designers occurs when none of the topologies tried are able to meet target performances and yield. The designer may have even tried to apply an automated performance/yield optimizer to get the best possible designs, but to no avail. In this case, the designer may need to design a new topology. There are no industrially scalable automated topology design approaches, so topology design must be manual. Topology design requires deep insight into design and the issues related to past topologies, i.e., knowledge of why prior topologies that were tried did not work. A tool that provides information such as relative impacts of design variables and random variables on past topologies would be invaluable information to the designer as they try new topologies. Furthermore, such a tool would also be very useful in the new candidate topology designs that the designer attempts, to learn what its particular issues are.
Another problem is that the person who does the front-end design (e.g., topology selection or design, sizing) is often not the same person who does layout design. If they are different people, then the person doing the front-end design will have far more insight into the relative importance of variables/devices on performance (and to a lesser extent, yield) because that is where their training lies. But the person doing the layout design may still need to make changes, to resolve layout-related yield issues, parasitic issues, and more. Unfortunately, when they make changes to the design they may inadvertently affect the performance or the yield of the circuit, without realizing it. Further, even if they did notice the problem, they would not necessarily have the insight to know what they can and cannot change.
To improve the insight that designers have into their circuits, it would be very useful to have a mechanism to determine how much each individual device affects yield and/or performance; and to have that info across a range of design space broader than sensitivity analysis (which is by definition local). Further, a mechanism to determine the interactions between components and how they affect performance and/or yield would be very useful. It would also be very useful to know this information not only on a component-by-component basis, but also at the level of design variables (e.g., width), random variables (e.g., oxide thickness of a given device), and environmental variables (e.g., power supply voltage, load resistance, temperature, etc.).
Therefore, it is desirable to provide a tool for extracting and presenting information to a designer to convey how individual elements (devices or variables) can affect the performance and/or yield of an electrical circuit design. This desired tool should be able to perform on an element-by-element basis, or by taking into account coupling between elements. Furthermore, it is desirable to provide a general means for the designer to gain insight by extracting knowledge from circuit simulation data, including: identifying causal variable dependencies of circuit variables (and thus circuit devices too); identifying interesting clusters of circuit simulation data (e.g. clusters of metric values); reducing dimensionality into human-viewable dimensions; and visually representing the extracted knowledge.